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PH6030L N-channel TrenchMOS logic level FET Rev. 01 -- 29 July 2008 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features and benefits Lead-free package Logic level compatibile Optimized for use in DC-to-DC converters Very low switching and conduction losses 1.3 Applications DC-to-DC convertors Notebook computers Switched-mode power supplies Voltage regulators 1.4 Quick reference data Table 1. VDS ID Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1; see Figure 3 VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 11; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 Min Typ Max 30 76.7 Unit V A drain-source voltage Tj 25 C; Tj 150 C drain current Symbol Parameter Dynamic characteristics QGD gate-drain charge 3.1 nC Static characteristics RDSon drain-source on-state resistance 4.7 6 m NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1, 2, 3 4 mb S G D Pinning information Symbol Description source gate mounting base; connected to drain 1234 mb D Simplified outline Graphic symbol G mbb076 S SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name PH6030L LFPAK Description Version Plastic single-ended surface-mounted package (LFPAK); SOT669 4 leads 4. Limiting values Table 4. Symbol VDS VDGR VGS ID Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1; see Figure 3 IDM Ptot Tstg Tj IS ISM EDS(AL)S peak drain current total power dissipation storage temperature junction temperature source current peak source current non-repetitive drain-source avalanche energy Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 10 V; Tj(init) = 25 C; ID = 31 A; Vsup 30 V; tp = 0.14 ms; RGS = 50 ; unclamped inductive load tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -20 -55 -55 Max 30 30 20 48.5 76.7 300 62.5 150 150 52 208 95 Unit V V V A A A W C C A A mJ In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode Avalanche ruggedness PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 2 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 120 Ider (%) 80 03aa23 120 Pder (%) 80 03aa15 40 40 0 0 50 100 150 Tmb (C) 200 0 0 50 100 150 Tmb (C) 200 Fig 1. Normalized continuous drain current as a function of mounting base temperature 103 ID (A) 102 Limit RDSon = VDS / ID Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aab245 tp = 10 s 100 s 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 1 10 VDS (V) 102 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 3 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions see Figure 4 Min Typ Max 2 Unit K/W 10 Zth(j-mb) (K/W) 1 = 0.5 0.2 0.1 10-1 0.05 0.02 single pulse tp T P 003aab246 = tp T t 10 -2 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 4 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage Conditions ID = 250 A; VGS = 0 V; Tj = -55 C ID = 250 A; VGS = 0 V; Tj = 25 C Min 27 30 0.8 1.3 ID = 25 A; VDS = 12 V; see Figure 11; see Figure 12 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 Coss Crss output capacitance reverse transfer capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 Typ 1.7 8.5 7.3 4.7 1.75 15.2 14 8.5 3.1 4.1 4.4 3.5 2260 2540 460 210 Max 2.6 2.15 1 100 100 100 10.6 9.7 6 Unit V V V V V A A nA nA m m m nC nC nC nC nC nC V pF pF pF pF Static characteristics gate-source threshold ID = 1 mA; VDS = VGS; Tj = -55 C; see voltage Figure 7 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 7 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 7; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 150 C VGS = 16 V; VDS = 0 V; Tj = 25 C VGS = -16 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 150 C; see Figure 9 VGS = 4.5 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 RG QG(tot) gate resistance total gate charge f = 1 MHz ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 11; see Figure 12 ID = 0 A; VDS = 0 V; VGS = 4.5 V; see Figure 11 Dynamic characteristics QGS QGD QGS1 QGS2 VGS(pl) Ciss gate-source charge gate-drain charge pre-threshold gate-source charge post-threshold gate-source charge gate-source plateau voltage input capacitance ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 12 PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 5 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET Table 6. Symbol td(on) tr td(off) tf VSD trr Qr Characteristics ...continued Parameter turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 14 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 30 V IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V Conditions VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG(ext) = 5.6 Min Typ 25 53 27 14 0.85 34 11.5 Max 1.2 Unit ns ns ns ns V ns nC Source-drain diode 100 ID (A) 80 003aab247 VGS (V) = 10 6 5 4.5 100 ID (A) 80 003aab249 4 60 3.6 40 3.4 3.2 20 3 2.8 0 0 0.2 0.4 0.6 VDS (V) 0.8 60 40 20 Tj = 150 C 25 C 0 0 1 2 3 4 VGS (V) 5 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 6 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 3 VGS(th) (V) max 2 typ 1.5 min 1 003aab272 10-3 ID (A) 10-4 min typ 003aab271 max 10-5 0.5 0 -60 10-6 0 60 120 Tj (C) 180 0 0.5 1 1.5 2 2.5 VGS (V) Fig 7. Gate-source threshold voltage as a function of junction temperature 2 a 1.6 003aab273 Fig 8. Sub-threshold drain current as a function of gate-source voltage 16 RDSon (m) 12 003aab248 3.2 3.4 3.6 VGS (V) = 4 1.2 8 0.8 4 0.4 4.5 5 6 10 0 -60 0 0 60 120 Tj (C) 180 0 20 40 60 80 ID (A) 100 Fig 9. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 10. Drain-source on-state resistance as a function of drain current; typical values PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 7 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET VDS ID VGS(pl) 10 VGS ID = 25 A Tj = 25 C (V) 8 12 V 6 003aab250 VDS = 19 V VGS(th) VGS QGS1 QGS2 QGD QG(tot) 003aaa508 4 QGS 2 Fig 11. Gate charge waveform definitions 0 0 10 20 30 QG (nC) 40 Fig 12. Gate-source voltage as a function of gate charge; typical values 104 C (pF) Ciss 60 10 3 003aab252 100 IS (A) 80 003aab251 40 Coss 20 Crss 10 2 150 C Tj = 25 C 10-1 1 10 VDS (V) 102 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig 14. Source current as a function of source-drain voltage; typical values PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 8 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 L1 A c2 A2 C E1 b3 mounting base D1 H D b4 L2 1 e 2 3 b 1/2 4 wM A c X e A A1 C (A 3) detail X L yC 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 0.25 0.30 4.10 4.20 0.19 0.24 3.80 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 Fig 15. Package outline SOT669 (LFPAK) PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 9 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Release date 20080729 Data sheet status Product data sheet Change notice Supersedes Document ID PH6030L_1 PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 10 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PH6030L_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 29 July 2008 11 of 12 NXP Semiconductors PH6030L N-channel TrenchMOS logic level FET 11. Contents 1. 1.1 1.2 1.3 1.4 2. 3. 4. 5. 6. 7. 8. 9. 9.1 9.2 9.3 9.4 10. Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 July 2008 Document identifier: PH6030L_1 |
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